Today more than ever, we need high-speed circuits with low occupancy and low power as an alternative to CMOS circuits. Therefore, we proposed a new path to build nanoscale circuits such as Quantum-dot Cellular Automata (QCA). This technology is always prone to failure due to its very small size. Therefore, designers always try to design fault-tolerant gates and provide methods to increase the reliability of QCA. By adding redundant cells, the possibility of some defects such as cell omission and cell addition is somewhat reduced. However, in the face of defects such as stuck-at 0/1 faults, Clock fault and bridging fault. We can greatly increase the fault tolerance by appropriate placement and using fault tolerant gates with a suitable structure. In this paper, we design the XOR/XNOR gate with the approach of preventing stuck-at 0/1 fault, clock fault, and bridging fault using the first NNI gate tolerating cell addition fault.

In this article, a two-dimensional photonic crystal-based XOR gate is designed and simulated. For this purpose, an initial two-dimensional photonic crystal structure is chosen and waveguides are created for inputs and outputs. Then, defect rods are selected so that the obtained outputs are approximately consistent with the XOR gate truth table. After that, we will be looking for the best output so that the highest optical power is created for logic 1 and the lowest power in the logical state of 0. For this reason, the simulation is performed for four defect rods and the output is obtained for different the radius of the rods. Then, using the K-Nearest Neighbors algorithm, which is a machine learning algorithm, the best output for logic 0 and also for logic 1 is obtained. The results show that the designed logic gate has high output power in logic 1 and very low power in the logic 0 state.

The aim of this paper is to suggest new and efficient designs for XOR circuits based on nanomagnetic logic technology in order to implementation of nanomagnetic computational circuits such as adders, subtractors and multipliers. Nanomagnetic logic due to its properties such as very high speed, low power consumption, scalability and working on room temperature is a suitable alternative for conventional transistor technology. First, nanomagnetic majority gates are introduced then two efficient designs with minimum area, minimum number of nanomagnetic elements and lowest delays for XOR circuits are proposed based on a three-input minority gate and a five-input majority gate. Basic elements in these designs are out-of-plane nanomagnetic cells made of Co/Pt, due to relative advantages of this alloy. Clocking field which is an external uniform magnetic field is required for proper performance of these proposed circuits. MagCAD tool was used for implementation of these designs, and the accuracy of operation of these circuits was proved by applying Modelsim simulator. According to the results of this simulation, it is shown that the proposed single layer and multilayer three-input XOR gates have improvement in comparison to the state-of-art design in number of gates 50% and 25%, in delay 80% and 80%, and in the number of elements 23% and 21%, respectively.

In this paper a novel all-optical logic NAND, NOR and XOR gate based on nonlinear directional coupler theory is demonstrated. We use the identical structure which contains three waveguides, for designing these gates, the only difference however, is the power of inputs light beam. In other words, while a beam with 4 W/mm in power considered as logical one, the output is NAND gate and if a beam with 6 W/mm in power considered as logical one, the same output, will be represented, the NOR function. In this case, an other waveguide of the structure is represented the XOR gate. Therefore this case, shows both NOR/XOR gates simultaneously. By use of three waveguides and adjusting the refractive index of waveguides and selecting the proper waveguide length, NAND/NOR/XOR gates can be obtained. The operation of these gates is simulated by use of R soft's Beam PROP simulator.

Over the years, the design and implementation of fault-tolerant circuits have been one of the main concerns of the designers of electronic devices. Quantum Dot Cellular Automata (QCA) is a low-power, compact technology that is prone to various defects due to its small size. We can categorize these defects into three main groups: operational defects, manufacturing defects, and clocking defects. Using redundant cells, fault-tolerant gates, or changing the structure of the gates can improve the overall fault-tolerance of the circuit in some cases. However, increasing the fault-tolerance would lead to an increase in the occupied area and the delay of the gates. Therefore, designing a gate based on intercellular interactions with a minimum number of cells and maximum efficiency, which is also fault-tolerant, is a challenging task. In this paper, we present a new tile-shaped design for XOR and XNOR gates that is robust to the Missing cell, Extra cell, and Rotated cell defects by 25%, 55%, and 25%, respectively. That is why we call these gates TFXOR and TFXNOR, respectively.

Since, the characteristics of VLSI basic circuits like XOR/XNOR which are the result of single cell simulation setup, are not necessarily defining their behavior in multistage circuits, so reaching to different test methods and more suitable patterns are important issues for investigators in this field. In this paper a new method is proposed in which timing behavior of different circuits can be determined and compared so the result can be used in different structure configurations and large scale circuits. In addition to the new algorithm for designing XOR/XNOR balance circuits, two more new circuits have been proposed. By simulation tool, HSPICE, first sizing transistor due to PDP characteristics for circuits has been done and then their timing behaviors have been compared. The optimal circuit due to timing behavior is one of the novel methods. Simulations have been done by 0.18mm tmtechnology on the base of BS2M3v model.